Samsung S3C2451X User Manual page 213

S3C2451X RISC MICROPROCESSOR
Demand/Handshake Mode Comparison
These are two different modes related to the protocol between XnXDREQ and XnXDACK. Figure. 9-2 shows the
differences between these two modes i.e., Demand and Handshake modes.
At the end of one transfer (Single/Burst transfer), DMA checks the state of double-synched XnXDREQ.
Demand mode
•
If XnXDREQ remains asserted, the next transfer starts immediately. Otherwise it waits for XnXDREQ to be
asserted.
Handshake mode
•
If XnXDREQ is deasserted, DMA deasserts XnXDACK in 2cycles. Otherwise it waits until XnXDREQ is
deasserted.
Caution: XnXDREQ has to be asserted (low) only after the deassertion (high) of XnXDACK.
XSCLK
Demand Mode
XnXDREQ
XnXDACK
Handshake Mode
XnXDREQ
XnXDACK
–
1st Transfer
Double
synch
BUS Acquisiton
Figure 9-2. Demand/Handshake Mode Comparison
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Related to the Protocol between XnXDREQ and XnXDACK
2cycles
Read Write
Actual Transfer
Read Write
2cycles
DMA CONTROLLER
2nd Transfer
Read Write
Double
synch
2cycles
9-5