Samsung S3C2451X User Manual page 660

IIS-BUS INTERFACE
The Data is aligned in the TX FIFO for 24-bits/channel BLC as shown
31
INVALID
INVALID
INVALID
INVALID
Once the data is written to the TX FIFO the TX channel can be made active by enabling the I2SACTIVE bit
in the I2SCON Register (I2S Control Register).
The data is then serially shifted out with respect to the bit clock SCLK and word select clock LRCLK.
The TXCHPAUSE in the I2SCON Register (I2S Control Register) can stop the serial data transmission on
the I2SSDO.The transmission is stopped once the current Left/Right channel is transmitted.
If the control registers in the I2SCON Register (I2S Control Register) and I2SMOD Register (I2S Mode
Register) are to be reprogrammed then it is advisable to disable the TX channel.
If the TX channel is enabled while the FIFO is empty, no samples are read from the FIFO.
The Status of TX FIFO can be checked by checking the bits in the I2SFIC Register (I2S FIFO Control
Register).
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
25-10
Specifications and information herein are subject to change without notice.
23
Figure 25-5: TX FIF0 Structure for BLC = 10 (24-bits/channel)
BLC = 10 (24-bits/channel)
LEFT CHANNEL
RIGHT CHANNEL
LEFT CHANNEL
RIGHT CHANNEL
S3C2451X RISC MICROPROCESSOR
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