Samsung S3C2451X User Manual page 696

AC97 CONTROLLER
AC-LINK OUTPUT FRAME (SDATA_OUT)
Slot 0: Tag Phase
In slot 0, the first bit is a bit (SDATA_OUT, bit 15) which represents the validity of the entire frame. If bit 15 is a 1,
the current frame contains at least a valid time slot. The next 12 bit positions correspond each 12 time slot
contains valid data. Bits 0 and 1 of slot 0 are used as CODEC IO bits for I/O reads and writes to the CODEC
registers as described in the next section. In this way, data streams of differing sample rate can be transmitted
across AC-link at its fixed 48kHz audio frame rate.
Slot 1: Command Address Port
In slot 1, it communicates control register address and write/read command information to the AC97 controller.
When software accesses the primary CODEC, the hardware configures the frame as follows :
- In slot 0, the valid bit for 1, 2 slots are set.
- In slot 1, bit 19 is set (read) or clear(write). Bits 18-12 (of slot 1) are configured to specify the index to the
CODEC register. Others are filled with 0's(reserved).
- In slot 2, it configured with the data which is for writing because of output frame.
Slot 2: Command Data Port
In slot 2, this is the write data with 16-bit resolution.([19:4] is valid data)
Slot 3: PCM Playback Left channel
Slot 3 which is audio output frame is the composite digital audio left stream. If a sample has a resolution that is
less than 16 bits, the AC97 controller fills all training non-valid bit positions in the slot with zeroes.
Slot 4: PCM Playback Right channel
Slot 4 which is audio output frame is the composite digital audio right stream. If a sample has a resolution that is
less than 16 bits, the AC97 controller fills all training non-valid bit positions in the slot with zeroes.
SYNC
AC '97 samples SYNC assertion here
AC '97 Controller samples first SDATA_OUT bit of frame here
BIT_CLK
Valid
SDATA_OUT
Frame
END of previous Audio Frame
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
27-6
Specifications and information herein are subject to change without notice.
Tag Phase
Slot(1) Slot(2) Slot(12)
Figure 27-5. AC-link Output Frame
48KHz
12.288MHz
"0" "0"
"0" 19
(ID1) (ID0)
START of Data phase
Slot# 1
S3C2451 RISC MICROPROCESSOR
Data Phase
0 19
END of Data Frame
0
Slot# 12