Samsung S3C2451X User Manual page 363

S3C2451 RISC MICROPROCESSOR
UART ERROR STATUS REGISTER
There are four UART Rx error status registers including UERSTAT0, UERSTAT1, UERSTAT2 and UERSTAT3 in
the UART block.
Register
UERSTAT0 0x50000014
UERSTAT1 0x50004014
UERSTAT2 0x50008014
UERSTAT3 0x5000C014
UERSTATn
Break Detect
Frame Error
Parity Error
Overrun Error
NOTE: These bits (UERSATn[3:0]) are automatically cleared to 0 when the UART error status register is read.
Address R/W
R UART channel 0 Rx error status register
R UART channel 1 Rx error status register
R UART channel 2 Rx error status register
R UART channel 3 Rx error status register
Bit
[3] Set to 1 automatically to indicate that a break signal has been
received.
0 = No break receive
1 = Break receive (Interrupt is requested.)
[2] Set to 1 automatically whenever a frame error occurs during
receive operation.
0 = No frame error during receive
1 = Frame error (Interrupt is requested.)
[1] Set to 1 automatically whenever a parity error occurs during
receive operation.
0 = No parity error during receive
1 = Parity error (Interrupt is requested.)
[0] Set to 1 automatically whenever an overrun error occurs during
receive operation.
0 = No overrun error during receive
1 = Overrun error (Interrupt is requested.)
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Description
UART
Reset Value
0x0
0x0
0x0
0x0
Initial State
0
0
0
0
15-15