Samsung S3C2451X User Manual page 79

S3C2451X RISC MICROPROCESSOR
POWER MANAGEMENT
The power management block controls the system clocks by software for the reduction of power consumption in
S3C2451X. These schemes are related to PLL, clock control logic(ARMCLK, HCLK, PCLK) and wake-up signal.
S3C2451X has four power-down modes. The following section describes each power management mode.
Related registers are PWRMODE, PWRCFG and WKUPSTAT.
POWER MODE STATE DIAGRAM
Figure 2-10 shows that Power Saving mode state and Entering or Exiting condition. In general, the entering
conditions are set by the main CPU.
IDLE
CMD
One of
wakeup
source
CMD
Figure 2-10. Power mode state diagram
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Norm al
(General Clock
Gating Mode)
One of
wakeup
source
Reset
or
restricted
wakeup
evants.
SLEEP
SYSTEM CONTROLLER
CM D
STOP
or DEEP-STOP
2-13