Samsung S3C2451X User Manual page 146

MOBILE DRAM CONTROLLER
3) DDR2 memory EMRS(2)[31:16]
PnBANKCON
BA [31:30]
Reserved [29:24]
SRF
Reserved [22:20]
DCC
PASR [18:16]
4) DDR2 memory EMRS(3)[31:16]
PnBANKCON
BA [31:30]
Reserved [29:16]
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
6-14
Specifications and information herein are subject to change without notice.
Bit
Bank address for EMRS
Should be '0'
High Temperature Self-Refresh Rate Enable
[23]
0 = Disable 1 = Enable
Should be '0'
[19] 0 = Disable 1 = Enable
PASR(Partial Array Self Refresh) for EMRS(2)
Bit
Bank address for EMRS
Should be '0'
S3C2451X RISC MICROPROCESSOR
Description
Description
Initial State
10b
000000b
0b
000b
0b
000b
Initial State
10b
0x0