Samsung S3C2451X User Manual page 411

S3C2451X RISC MICROPROCESSOR
SDA
MSB
SCL
S
ACK SIGNAL TRANSMISSION
To complete a one-byte transfer operation, the receiver should send an ACK bit to the transmitter. The ACK pulse
should occur at the ninth clock of the SCL line. Eight clocks are required for the one-byte data transfer. The
master should generate the clock pulse required to transmit the ACK bit.
The transmitter should release the SDA line by making the SDA line High when the ACK clock pulse is received.
The receiver should also drive the SDA line Low during the ACK clock pulse so that the SDA keeps Low during
the High period of the ninth SCL pulse.
The ACK bit transmit function can be enabled or disabled by software (IICSTAT). However, the ACK pulse on the
ninth clock of SCL is required to complete the one-byte data transfer operation.
Data Output by
Transmitter
Data Output by
Receiver
SCL from
Master
Condition
Acknowledgement
Signal from Receiver
1 2 7
Byte Complete, Interrupt
within Receiver
Figure 18-4. Data Transfer on the IIC-Bus
1
S
Start
Figure 18-5. Acknowledge on the IIC-Bus
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
8 9 1
ACK
2
Acknowledgement
Signal from Receiver
2 9
Clock Line Held Low by
receiver and/or transmitter
Clock to Output
7 8
Clock Pulse for Acknowledgment
IIC-BUS INTERFACE
9
18-5