Samsung S3C2451X User Manual page 155

S3C2451X RISC MICROPROCESSOR
7.10.4 4-BIT ECC PROGRAMMING GUIDE (DECODING)
1. To use 4-bit ECC, set the MsgLength to 0(512-byte message length) and set the ECCType to '1'(enable 4-bit
ECC). ECC module generates ECC parity code for 512-byte read data. So, you have to reset ECC value by
writing the InitMECC (NFCONT[5]) bit as '1' and have to clear the MainECCLock (NFCONT[7]) bit to
'0'(Unlock) before read data.
MainECCLock (NFCONT[7]) bit controls whether ECC Parity code is generated or not.
2. Whenever data is read, the 4-bit ECC module generates ECC parity code internally.
3. After you complete read 512-byte (does not include spare area data), you have to read parity codes. 4-bit
ECC module needs parity codes to detect whether error bits are or not. So you have to read ECC parity code
right after read 512-byte. Once ECC parity code is read, 4-bit ECC engine start to search any error internally.
4-bit ECC error searching engine need minimum 155 cycles to find any error. During this time, you can
continue read main data from external NAND flash memory. ECCDecDone(NFSTAT[6]) can be used to check
whether ECC decoding is completed or not.
4. When ECCDecDone (NFSTAT[6]) is set ('1'), NFECCERR0 indicates whether error bit exist or not. If any
error exists, you can fix it by referencing NFECCERR0/1 and NFMLCBITPT register.
5. If you have more main data to read, continue to step 2.
6. For meta data error check, set the MsgLength to 1(24-byte message length) and set the ECCType to
'1'(enable 4-bit ECC). ECC module generates ECC parity code for 24-byte read data. So you have to reset
ECC value by writing the InitMECC (NFCONT[5]) bit as '1' and have to clear the MainECCLock (NFCONT[7])
bit to '0'(Unlock) before read data.
MainECCLock (NFCONT[7]) bit controls whether ECC Parity code is generated or not.
7. Whenever data is read, the 4-bit ECC module generates ECC parity code internally.
8. After you complete read 24-byte, you have to read parity codes. 4-bit ECC module needs parity codes to
detect whether error bits are or not. So you have to read ECC parity codes right after read 24-byte. Once ECC
parity code is read, 4-bit ECC engine start to search any error internally. 4-bit ECC error searching engine
need minimum 155 cycles to find any error. During this time, you can continue read main data from external
NAND flash memory. ECCDecDone(NFSTAT[6]) can be used to check whether ECC decoding is completed
or not.
9. When ECCDecDone (NFSTAT[6]) is set ('1'), NFECCERR0 indicates whether error bit exist or not. If any
error exists, you can fix it by referencing NFECCERR0/1 and NFMLCBITPT register.
7.10.5 8-BIT ECC PROGRAMMING GUIDE (ENCODING)
1. To use 8-bit ECC in software mode, set the MsgLength to 0(512-byte message length) and set the ECCType
to "01"(enable 8-bit ECC). ECC module generates ECC parity code for 512-byte write data. In order to start
the ECC module, you have to write '1' on the InitMECC (NFCONT[5]) bit after cleaning the MainECCLock
(NFCONT[7]) bit to '0' (Unlock).
MainECCLock (NFCONT[7]) bit controls whether ECC Parity code is generated or not.
Note. In 8bit ECC, MainECCLock should be cleared before initiating InitMECC.
2. Whenever data is written, the 8bit ECC module generates ECC parity code internally.
3. After you finish writing 512-byte data (not include spare area data), the parity codes are automatically updated
to NF8MECC0, NFMECC1, NF8MECC2, NF8MECC3 register. If you use 512-byte NAND flash memory, you
can program these values directly to spare area. However, if you use NAND flash memory more than 512-
byte page, you can't program immediately. In this case, you have to copy these parity codes to other memory
like DRAM. After writing all main data, you can write the copied ECC values to spare area.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
NAND FLASH CONTROLLER
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