S3C2451X RISC MICROPROCESSOR
PORT J CONTROL REGISTERS (GPJCON, GPJDAT, GPJUDP, GPJSEL) (Continued)
GPJDAT
Reserved
GPJ[15:0]
GPJUDP
GPJUDP15
~
GPJUDP0
GPJSEL
Reserved
GPJ13SEL
Bit
[31:16]
Reserved
[15:0]
When the port is configured as an input port, the corresponding bit is the
pin state. When the port is configured as an output port, the pin state is the
same as the corresponding bit.
When the port is configured as functional pin, the undefined value will be
read.
Bit
[CPU:CPD]
[31:30]
~
00 : pull-up/down disable
[1:0]
01 : pull-down enable
10 : pull-up enable
11 : not-available
Bit
[31:1]
Reserved
[0]
0 = GPJ13
Description
Description
Description
1 = PCM1_FSYNC
I/O PORTS
11-27