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IIS-BUS INTERFACE
RXCHPAUSE
TXDMACTIVE
RXDMACTIVE
I2SACTIVE
NOTES:
1)
When playing is finished, overrun interrupt will be occur. (Since no more data are written into TXFIFO at
the end of playing.) User can stop transmission at this overrun interrupt.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
25-16
Specifications and information herein are subject to change without notice.
activated at any time, the channel operation will be halted after left-
right channel data transfer is completed.
0: No pause operation
1: Pause operation
[3]
R/W
Rx channel operation pause command. Note that when this bit is
activated at any time, the channel operation will be halted after left-
right channel data transfer is completed.
0: No pause operation
1: Pause operation
[2]
R/W
Tx DMA active (start DMA request). Note that when this bit is set
from high to low, the DMA operation will be forced to stop
immediately.
0: Inactive, 1: Active
[1]
R/W
Rx DMA active (start DMA request). Note that when this bit is set
from high to low, the DMA operation will be forced to stop
immediately.
0: Inactive, 1: Active
[0]
R/W
IIS interface active (start operation).
0: Inactive, 1:Active
S3C2451X RISC MICROPROCESSOR
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