Samsung S3C2451X User Manual page 81

S3C2451X RISC MICROPROCESSOR
STOP mode Exiting sequence is as follows
1. Enable X-tal Oscillator if it is used, and wait the OSC settle down (around 1ms).
2. After the Oscillator settle-down, the System Clock is fed using the PLL input clock and also enable the
PLLs and waits the PLL locking time
3. Switching the clock source, now the PLL is the clock source.
4. When waking up from Deep-STOP mode, ARM_PWRENn is restored to release ARM power gating. After
producing SYSCLK ARM_RESETn will be released to let ARM work nomally.
NOTE. DRAM has to be in self-refresh mode during STOP and SLEEP mode to retain valid memory data. LCD must be
stopped before STOP and SLEEP mode, because DRAM can't be accessed when it is in self-refresh mode.
SLEEP MODE
In the SLEEP Mode, all the clock sources are off and also the internal logic-power is not supplied except for the
wake-up logic circuitry. In this mode, the static power-dissipation of internal logic can be minimized.
SLEEP Mode Entering sequence is as follows.
1. User writes commnad into the system controller's PWRMODE[15:0] register to let system enter into the
SLEEP Mode.
2. System controller requests bus controller to finish bus transactions of ARM Core.
3. System controller disable ARM clock after getting ARM Down acknowledge.
4. System controller requests bus controller to finish current transactions.
5. Bus controller send acknowledge to system controller after completed bus transactions.
6. System controller request memory controller to enter self refresh mode. It is for preserving contents in
SDRAM.
7. System controller wait for self refresh acknowledge from memory controller.
8. After receiving the self-refresh acknowledge, System controller disable system clocks(HCLK, PCLK and
so on).
9. System controller asserts control signals to mask unknown state of ALIVE logics and to preserve data of
retention Pads.
10. System controller asserts PWR_EN pin and disables the X-tal and PLL oscillation. PWR_EN pin is used
to indicate the readiness for external power OFF and to enable and disable of of the power regulator
which produces internal-logic power.
SLEEP Mode Exiting sequence is as follows.
1. System controller enable external power source by deactivation of the PWR_EN pin and wait power settle
down time (it is programmable by a register in the PWRSETCNT field of RSTCON register).
2. System controller asserts HRESETn and consequently all bus down, self refresh requests and
acknowledge signals will be their reset state.
3. System controller release the HRESETn(synchronously, relatively to the system clock) after the power
supply is stabilized.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
SYSTEM CONTROLLER
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