Samsung S3C2451X User Manual page 368

UART
Floating point part
0
0.0625
0.125
0.1875
0.25
0.3125
0.375
0.4375
0.5
0.5625
0.625
0.6875
0.75
0.8125
0.875
0.9375
Baud-Rate Error Tolerance
UART Frame error should be less than 1.87%(3/160).
tUPCLK = (UBRDIVn + 1) x 16 x 1Frame / PCLK
tEXTUARTCLK = 1Frame / baud-rate
UART error = (tUPCLK – tEXTUARTCLK) / tEXTUARTCLK x 100%
NOTE:
1Frame = start bit + data bit + parity bit + stop bit.
Error Tolerance is calculated from the timing of reading stop bit at Ideal UART clock vs Real UART clock.
From the Ideal UART clock reading stop bit timing ± 3 clock period of 16 times the baud-rate are allowed.
UART Clock and PCLK Relation
here is a constraint on the ratio of clock frequencies for PCLK to UARTCLK.
The frequency of UARTCLK must be no more than 5.5/3 times faster than the frequency of PCLK :
F <= 5.5/3 X F
UARTCLK
This allows sufficient time to write the received data to the receive FIFO
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
15-20
Specifications and information herein are subject to change without notice.
Table 15-2 Recommended value table of DIVSLOTn register
Num of 1's
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
PCLK
0x0000(0000_0000_0000_0000b)
0x0080(0000_0000_0000_1000b)
0x0808(0000_1000_0000_1000b)
0x0888(0000_1000_1000_1000b)
0x2222(0010_0010_0010_0010b)
0x4924(0100_1001_0010_0100b)
0x4A52(0100_1010_0101_0010b)
0x54AA(0101_0100_1010_1010b)
0x5555(0101_0101_0101_0101b)
0xD555(1101_0101_0101_0101b)
0xD5D5(1101_0101_1101_0101b)
0xDDD5(1101_1101_1101_0101b)
0xDDDD(1101_1101_1101_1101b)
0xDFDD(1101_1111_1101_1101b)
0xDFDF(1101_1111_1101_1111b)
0xFFDF(1111_1111_1101_1111b)
tUPCLK: Real UART Clock
tEXTUARTCLK: Ideal UART Clock
F = baudrate x 16
UARTCLK
S3C2451 RISC MICROPROCESSOR
UDIVSLOTn