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S3C2451X RISC MICROPROCESSOR
BASIC TIMER OPERATION
A timer (except the timer ch-4) has TCNTBn, TCNTn, TCMPBn and TCMPn. The TCNTBn and the TCMPBn are
loaded into the TCNTn and the TCMPn when the timer reaches 0.
When the TCNTn reaches 0, an interrupt request will occur if the interrupt is enabled.
TCNTn and TCMPn are the names of the internal registers. (16bit Internal down-counter (register) and
16bit internal compare register, respectively.) The TCNTn register can be read from the TCNTOn register
If you want to generate interrupt at intervals 3cycle of TOUTn, set TCNTBn, TCMPBn and TCON register like
Figure 13-2. That is :
i)
Set TCNTBn=3 and TCMPBn=1.
ii)
Set auto-reload=1 and manual update=1.
When manual update bit is 1, TCNTBn and TCMPBn value are loaded to TCNTn and TCMPn.
iii)
Set TCNTBn=2 and TCMPBn=0 for next operation.
iv)
Set auto-reload=1 and manual update=0.
If you set manual update=1 at this time, TCNTn is changed to 2 and TCMP is changed to 0.
So, interrupt is generated at interval 2cycle instead of 3cycle.
You must set auto-reload=1 automatically for next operation.
v)
Set start = 1 for operation start and then TCNTn is down counting.
When TCNTn is 0, interrupt is generated and If auto-reload is enable, TCNTn is loaded 2
(TCNTBn value) and TCMPn is loade 0(TCMPn value).
vi)
Before stop, TCNTn is down counting.
Figure 13-2. Timer Operations
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
NOTE:
PWM TIMER
13-3
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