Samsung S3C2451X User Manual page 94

SYSTEM CONTROLLER
The AHB and APB clocks are en/disabled by HCLKCON register. All reserved bits have 1 value at initial state.
HCLKCON Bit
RESERVED [31:21]
2D [20]
DRAMC [19]
SSMC [18]
CFC [17]
HSMMC1 [16]
HSMMC0 [15]
RESERVED [14]
IROM [13]
USBDEV [12]
USBHOST [11]
[10]
RESERVED
DISPCON [9]
CAMIF [8]
DMA0~7 [7:0]
PCLKCON Bit
RESERVED [31:20]
PCM [19]
[18]
RESERVED
I2S_1 [17]
I2C_1 [16]
CHIP_ID [15]
SPI_HS_1 [14]
GPIO [13]
RTC [12]
WDT [11]
PWM [10]
I2S_0 [9]
AC97 [8]
TSADC [7]
SPI_HS_0 [6]
RESERVED [5]
I2C_0 [4]
UART0~3 [3:0]
Preliminary product information describe products that are in development,
2-28
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
-
Enable HCLK into 2D
Enable HCLK into DRAM controller
Enable HCLK into the SSMC block
Enable HCLK into the CF
Enable HCLK into the HSMMC1
Enable HCLK into the HSMMC0
-
Enable HCLK into the IROM
Enable HCLK into the USB device
Enable HCLK into the USB HOST
-
Enable HCLK into the display controller
Enable HCLK into the camera interface
Enable HCLK into DMA channel 0~7
-
Enable PCLK into the PCM
-
Enable PCLK into the I2S_1
Enable PCLK into the I2C_1
Enable PCLK into the CHIP_ID
Enable PCLK into the SPI_HS1 (into SPI2.0)
Enable PCLK into the GPIO
Enable PCLK into the RTC
Enable PCLK into the watch dog timer
Enable PCLK into the PWM
Enable PCLK into the I2S_0 (I2S
Enable PCLK into the AC97
Enable PCLK into the TSADC
Enable PCLK into the SPI_HS0 (HS
-
Enable PCLK into the I2C_0 (I2C
Enable PCLK into the UART0~3
S3C2451X RISC MICROPROCESSOR
Description
Description
I2S0)
HS0)
I2C0)
Initial Value
0x7FF
1
1
1
1
1
1
1
1
1
1
1
1
1
0xFF
Initial Value
0xFFF
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0xF