Samsung S3C2451X User Manual page 129

S3C2451X RISC MICROPROCESSOR
BANK CONTROL REGISTERS 0-5
Register
SMBCR0 0x4F000014
SMBCR1 0x4F000034
SMBCR2 0x4F000054
SMBCR3 0x4F000074
SMBCR4 0x4F000094
SMBCR5 0x4F0000B4
[31:26]
DELAYnCS [25:22]
AddrValid
WriteEn
BurstLenWrite [19:18]
SyncWriteDev
BMWrite
DRnOWE
Reserved
Reserved
AddrValid
ReadEn
BurstLen
[11:10]
Read
Address R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Read undefined. Write as zero.
Controls the delay between ADDR signal and nCS signal. The field
is valid only when DRnCS bit is 1.
[21] not available(should be high)
[20] Controls the behavior of the signal RSMAVD during write operations:
0: Signal always HIGH
1: Signal active for asynchronous and synchronous write accesses
(default).
Burst transfer length. Sets the number of sequential transfers that
the burst device supports for a write:
00: 4-transfer burst (default)
01: Reserved
10: Reserved
11: Reserved
[17] 0: Asynchronous device (default).
1: Synchronous device.
[16] Burst mode write:
0: Nonburst writes to memory devices (default at reset)
1: Burst mode writes to memory devices.
[15]
0: No delay (default)
1: Get the delay between nCS signal and nOE/nWE signal.
nOE: The number of cycle is defined by SMBWSTOENRx which
must be larger than 1.
nWE: The number of cycle is defined by SMBWSTWENRx which
must be larger than 1.
This bit is applied only when nWAIT signal is used.
[14] Reserved
[13] not available(should be high)
Controls the behavior of the signal RSMAVD during read operations:
[12]
0: Signal always HIGH.
1: Signal active for asynchronous and synchronous read accesses
(default).
Burst transfer length. Sets the number of sequential transfers that
the burst device supports for a read:
00: 4-transfer burst.
10: 16-transfer burst. 11: Reserved
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Bank0 control register
Bank1 control register
Bank2 control register
Bank3 control register
Bank4 control register
Bank5 control register
Description
01: 8-transfer burst.
STATIC MEMORY CONTROLLER
Reset Value
See note in p5-17
0x303000
0x303010
0x303000
0x303010
0x303010
Initial State
0x0
0x0
0x1
0x1
0x0
0x0
0x0
0x0
0x0
0x1
0x1
0x0
5-17