Samsung S3C2451X User Manual page 387

S3C2451X RISC MICROPROCESSOR
SCR Bit
[4]
SPDC [3]
MFRM [2]
HSUSPE [1]
HRESE [0]
R/W
Should be zero
Speed detection Control
R/W
Software can reset Speed detection Logic
through this bit.
This bit is used to control speed detection
process in case of System with a long initial time.
0: Enable
1: Disable
R/W Resume by MCU
If this bit is set, the suspended core generates a resume
signal. This bit is set when MCU writes 1. This bit is cleared
when MCU writes 0.
R/W Suspend Enable
When set to 1, core can respond to the suspend signaling
by USB host.
R/W Reset Enable
When set to 1, core can respond to the reset signaling by
USB host.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
USB2.0 DEVICE
Initial State
0
0
0
0
0
17-15