Samsung S3C2451X User Manual page 436

2D
FIFO INTERRUPT CONTROL REGISTER (FIFO_INTC_REG)
Register
FIFO_INTC_REG 0x4D408008
Field Bit
Reserved [31:6]
FIFO_INT_LEVEL [5:0]
INTERRUPT PENDING REGISTER (INTC_PEND_REG)
Register
INTC_PEND_REG 0x4D40800C
Field
Reserved
Reserved [30:11]
INTP_CMD_FIN
INTP_ALL_FIN
INTP_FULL
Reserved
INTP_FIFO_LEVEL
FIFO STATUE REGISTER (FIFO_STAT_REG)
Register
FIFO_STAT_REG 0x4D408010
Field
Reserved [31:11]
CMD_FIN
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
19-16
Address R/W
R/W FIFO Interrupt Control
If FIFO_INT_E (in INTEN_REG) is set, when FIFO_USED (in
FIFO_STAT_REG) is greater or equal to FIFO_INT_LEVEL, an
interrupt occurs.
Address R/W
R/W Interrupt Pending Register
Bit
Should be set '1'
[31]
Reserved
[10] Current Command Finished interrupt flag.
Writing '1' to this bit clears this flag.
[9] All Commands Finished interrupt flag.
Writing '1' to this bit clears this flag.
[8] Command FIFO Full interrupt flag.
Writing '1' to this bit clears this flag.
[7:1]
[0] FIFO_USED reaches FIFO_INT_LEVEL interrupt flag.
Writing '1' to this bit clears this flag.
Address R/W
R FIFO Status Register
Bit
[10] 1: The graphics engine finishes the execution of current command.
0: In the middle of rendering process.
S3C2451X RISC MICROPROCESSOR
Description
Description
Description
Description
Description
Description
Reset Value
0x18
Initial State
0x0
0x18
Reset Value
0x0
Initial State
-
-
-
-
-
-
Reset Value
0x600
Initial State
-
0x1