Samsung S3C2451X User Manual page 235

S3C2451X RISC MICROPROCESSOR
INTMSK2
INTPND2
INTOFFSET2
PRIORITY_MODE2
PRIORITY_UPDAT
E2
SOURCE PENDING (SRCPND) REGISTER
The SRCPND register is composed of 32 bits each of which is related to an interrupt source. Each bit is set to 1 if
the corresponding interrupt source generates the interrupt request and waits for the interrupt to be serviced.
Accordingly, this register indicates which interrupt source is waiting for the request to be serviced. Note that each
bit of the SRCPND register is automatically set by the interrupt sources regardless of the masking bits in the
INTMASK register. In addition, the SRCPND register is not affected by the priority logic of interrupt controller.
In the interrupt service routine for a specific interrupt source, the corresponding bit of the SRCPND register has to
be cleared to get the interrupt request from the same source correctly. If you return from the ISR without clearing
the bit, the interrupt controller operates as if another interrupt request came in from the same source. In other
words, if a specific bit of the SRCPND register is set to 1, it is always considered as a valid interrupt request
waiting to be serviced.
The time to clear the corresponding bit depends on the user's requirement. If you want to receive another valid
request from the same source, you should clear the corresponding bit first, and then enable the interrupt.
You can clear a specific bit of the SRCPND register by writing a data to this register. It clears only the bit positions
of the SRCPND corresponding to those set to one in the data. The bit positions corresponding to those that are
set to 0 in the data remains as they are.
Register
SRCPND 1 0X4A000000
SRCPND 2 0X4A000040
0X4A000048 R/W Determine which interrupt source of group 2 is
0X4A000050 R/W Indicate the interrupt request status for group 2.
0X4A000054 R
0x4A000070 R/W IRQ priority mode register 2
0x4A000074 R/W IRQ priority update register 2
Address R/W
R/W Indicate the interrupt request status for group 1.
0 = The interrupt has not been requested.
1 = The interrupt source has asserted the interrupt
request.
R/W Indicate the interrupt request status for group 2..
0 = The interrupt has not been requested.
1 = The interrupt source has asserted the interrupt
request.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
0 = IRQ mode 1 = FIQ mode
masked. The masked interrupt source will not be
serviced.
0 = Interrupt service is available.
1 = Interrupt service is masked.
0 = The interrupt has not been requested.
1 = The interrupt source has asserted the interrupt
request.
Indicate the IRQ interrupt request source for group
2
Description
INTERRUPT CONTROLLER
0xFFFFFFFF
0x00000000
0x00000000
0x00000000
0x7F
Reset Value
0x00000000
0x00000000
10-9