Samsung S3C2451X User Manual page 465

S3C2451X RISC MICROPROCESSOR
RxOverrun
RxUnderrun
TxOverrun
TxUnderrun
RxFifoRdy
TxFifoRdy
Register
HS_SPI_TX_DATA(Ch0)
HS_SPI_TX_DATA(Ch1)
HS_SPI_TX_DATA
TX_DATA
Register
HS_SPI_RX_DATA(Ch0)
HS_SPI_RX_DATA(Ch1)
HS_SPI_RX_DATA
RX_DATA
0 ~ 7'h40 byte
Rx Fifo overrun error
R
[5]
0: no error,
Rx Fifo underrun error
R
[4]
0: no error,
Tx Fifo overrun error
R
[3]
0: no error,
Tx Fifo underrun error
R 0: no error,
[2]
*If TX fifo empty, always occur at slave mode
0 : data in FIFO less than trigger level
R
1 : data in FIFO more than trigger level
[1]
0 : data in FIFO more than trigger level
R
[0]
1 : data in FIFO less than trigger level
Address R/W
0x52000018 W
0x59000018 W
Bit
This field contains the data to be transmitted over
W
[31:0]
the HS_SPI channel.
Address R/W
0x5200001C
0x5900001C
Bit
R
[31:0] This field contains the data to be received over
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
1: overrun error
1: underrun error
1: overrun error
1: underrun error
Description
HS_SPI TX DATA register
HS_SPI TX DATA register
Description
Description
R HS_SPI RX DATA register
R HS_SPI RX DATA register
Description
HS_SPI CONTROLLER
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
Reset Value
0x0
0x0
Initial State
32'b0
Reset Value
0x0
0x0
Initial State
32'b0
20-9