Samsung S3C2451X User Manual page 93

S3C2451X RISC MICROPROCESSOR
CLKDIV1 configures the clock ratio related on EPLL.
CLKDIV1
RESERVED [31:30]
CAMDIV [29:26]
SPIDIV_0 [25:24]
DISPDIV [23:16]
I2SDIV_0 [15:12]
UARTDIV [11:8]
HSMMCDIV_1 [7:6]
USBHOSTDIV
RESERVED [3:0]
CLKDIV2 configures the clock ratio related on EPLL or MPLL.
CLKDIV2
RESERVED [31:26]
SPIDIV1_EPLL [25:24]
RESERVED [23:21]
SPIDIV1_MPLL [20:16]
I2SDIV_1 [15:12]
RESERVED [11:8]
HSMMCDIV_0 [7:6]
RESERVED
SPIDIV0_MPLL [4:0]
Bit
-
CAM clock divider ratio.
ratio = CAMDIV + 1
HS-SPI clock divider ratio, ratio = (SPIDIV +1)
Display controller clock divider ratio,
ratio = (DISPDIV + 1)
I2S0 clock divider ratio, ratio = (I2SDIV_0 + 1)
UART clock divider ratio, ratio = (UARTDIV + 1)
HSMMC_1 clock divider ratio, ratio = (HSMMCDIV_1 + 1)
[5:4] Usb Host clock divider ratio, ratio = (USBHOSTDIV + 1)
-
Bit
-
HS-SPI_1 clock divider ratio(EPLL), ratio = (SPIDIV_1 +1)
-
HS-SPI1 clock divider ratio(MPLL), ratio = (SPIDIV_1 +1)
I2S1 clock divider ratio(EPLL), ratio = (I2SDIV_1 + 1)
HSMMC_0 clock divider ratio(EPLL), ratio = (HSMMCDIV_1 + 1)
[5] -
HS-SPI0 clock divider ratio(MPLL), ratio = (SPIDIV_1 +1)
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Description
-
SYSTEM CONTROLLER
Initial Value
0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0
Initial Value
0
0x0
0
0
0x0
0
0x0
0
0
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