Samsung S3C2451X User Manual page 513

S3C2451X RISC MICROPROCESSOR
STACARD [7]
REM
STACARDI [6]
NS
STABUFRD [5]
RDY
STABUFW [4]
TRDY
STADMAIN [3]
T
STABLKGA [2]
P
to the Host System. It is necessary to define how to handle this delay.
When this status has been set and the Host Driver needs to start this
interrupt service, Card Interrupt Status Enable in the Normal Interrupt
Status Enable register shall be set to 0 in order to clear the card interrupt
statuses latched in the Host Controller and to stop driving the interrupt signal
to the Host System. After completion of the card interrupt service (It should
reset interrupt factors in the SD card and the interrupt signal may not be
asserted), set Card Interrupt Status Enable to 1 and start sampling the
interrupt signal again. (ROC, RW1C)
'1' = Generate Card Interrupt
'0' = No Card Interrupt
Card Removal
This status is set if the Card Inserted in the Present State register changes
from 1 to 0. When the Host Driver writes this bit to 1 to clear this status, the
status of the Card Inserted in the Present State register should be confirmed.
Because the card detect state may possibly be changed when the Host Driver
clear this bit and interrupt event may not be generated. (RW1C)
'1' = Card removed
'0' = Card state stable or Debouncing
Card Insertion
This status is set if the Card Inserted in the Present State register changes
from 0 to 1. When the Host Driver writes this bit to 1 to clear this status, the
status of the Card Inserted in the Present State register should be confirmed.
Because the card detect state may possibly be changed when the Host Driver
clear this bit and interrupt event may not be generated. (RW1C)
'1' = Card inserted
'0' = Card state stable or Debouncing
Buffer Read Ready
This status is set if the Buffer Read Enable changes from 0 to 1. Refer to the
Buffer Read Enable in the Present State register. (RW1C)
'1' = Ready to read buffer
'0' = Not ready to read buffer
Buffer Write Ready
This status is set if the Buffer Write Enable changes from 0 to 1. Refer to
the Buffer Write Enable in the Present State register. (RW1C)
'1' = Ready to write buffer
'0' = Not ready to write buffer
DMA Interrupt
This status is set if the Host Controller detects the Host DMA Buffer
boundary during transfer. Refer to the Host DMA Buffer Boundary in the
Block Size register. Other DMA interrupt factors may be added in the future.
This interrupt shall not be generated after the Transfer Complete. (RW1C)
'1' = DMA Interrupt is generated
'0' = No DMA Interrupt
Block Gap Event
If the Stop At Block Gap Request in the Block Gap Control register is set,
this bit is set when both a read / write transaction is stopped at a block gap. If
Stop At Block Gap Request is not set to 1, this bit is not set to 1.
(1) In the case of a Read Transaction
This bit is set at the falling edge of the DAT Line Active Status (When the
transaction is stopped at SD Bus timing. The Read Wait must be supported in
order to use this function.
(2) Case of Write Transaction
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
HSMMC CONTROLLER
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0
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