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S3C2451X RISC MICROPROCESSOR
IIS MODE REGISTER (IISMOD)
Register
IISMOD
IISMOD
Reserved
CDD2
CDD1
DCE
BLC
CDCLKCON
IMS
Address
0x55000004
Bit
R/W
[31:15]
R/W
Reserved. Program to zero.
[21:20]
R/W
Channel-2 Data Discard. Discard means zero padding. It only
supports 8/16 bit mode.
00 : No Discard
01 : I2STXD[15:0] Discard
10 : I2STXD[31:16] Discard
11 : Reserved
[19:18]
R/W
Channel-1 Data Discard. Discard means zero padding. It only
supports 8/16 bit mode.
00 : No Discard
01 : I2STXD[15:0] Discard
10 : I2STXD[31:16] Discard
11 : Reserved
[17:16]
R/W
Data Channel Enable.
[17] : SD2 channel enable
[16] : SD1 channel enable
[15]
R/W
Reserved, Program to Zero
[14:13]
R/W
Bit Length Control Bit Which decides transmission of 8/16 bits per
audio channel
00:16 Bits per channel
01:8 Bits Per Channel
10:24 Bits Per Channel
11:Reserved
[12]
R/W
Determine direction of codec clock(I2SCDCLK)
0 : Supply codec clock to external codec chip.
(from PCLK, EPLL, EPLLRefCLK)
1 : Get codec clock from external codec chip.
(to CLKAUDIO)
(Refer to Figure 26-2)
[11:10]
R/W
IIS master or slave mode select. (and select source of codec clock)
00: Master mode
01: Master mode
(CLKAUDIO is source clock for I2SSCLK, I2SLRCLK.
10: Slave mode
11: Slave mode
(Refer to Figure 26-2)
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
IIS interface mode register
(PCLK is source clock for I2SSCLK, I2SLRCLK, I2SCDCLK)
CLKAUDIO-EPLL, EPLLRefCLK is source clock for I2SCDCLK)
(PCLK is source clock for I2SCDCLK)
(CLKAUDIO-EPLL, EPLLRefCLK is source clock for I2SCDCLK)
IIS MULTI AUDIO INTERFACE
Description
Reset Value
0x0000_0000
26-17
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