Samsung S3C2451X User Manual page 515

S3C2451X RISC MICROPROCESSOR
ERROR INTERRUPT STATUS REGISTER
Signals defined in this register can be enabled by the Error Interrupt Status Enable register, but not by the
Error Interrupt Signal Enable register. The interrupt is generated when the Error Interrupt Signal Enable is
enabled and at least one of the statuses is set to 1. Writing to 1 clears the bit and writing to 0 keeps the bit
unchanged. More than one status can be cleared at the one register write.
Register
ERRINTSTS0
ERRINTSTS1
Name Bit
[15:10] Reserved
ADMA Error
ADMAER [9]
R This bit is set when the Host Controller detects errors during ADMA based
data transfer. The state of the ADMA at an error occurrence is saved in the
ADMA Error Status Register, In addition, the Host Controller generates this
Interrupt when it detects invalid descriptor data (Valid=0) at the ST_FDS
state. ADMA Error State in the ADMA Error Status indicates that an error
occurs in ST_FDS state. The Host Driver may find that Valid bit is not set at
the error descriptor.
'1' = Error
'0' = No Error
Auto CMD12 Error
STAACM [8]
DERR
register has changed from 0 to 1. This bit is set to 1,not only when the errors
in Auto CMD12 occur but also when Auto CMD12 is not executed due to the
previous command error.
'1' = Error
'0' = No Error
STACUR [7] Current Limit Error
ERR
Data End Bit Error
STADEN [6]
Occurs either when detecting 0 at the end bit position of read data which
DERR
uses the DAT line or at the end bit position of the CRC Status.
'1' = Error
'0' = No Error
Data CRC Error
STADAT [5]
Occurs when detecting CRC error when transferring read data which uses
CRCER
the DAT line or when detecting the Write CRC status having a value of other
R
than "010".
'1' = Error
'0' = No Error
Data Timeout Error
STADAT [4]
Occurs when detecting one of following timeout conditions.
TOUTER
(1) Busy timeout for R1b,R5b type
Address
0X4AC00032 ROC/RW1C
0X4A800032 ROC/RW1C
Occurs when detecting that one of the bits in Auto CMD12 Error Status
Not implemented in this version. Always 0.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
R/W
Error Interrupt Status Register (Channel 0)
Error Interrupt Status Register (Channel 1)
Description
HSMMC CONTROLLER
Description Reset Value
0x0
0x0
Initial
Value
0
0
0
0
0
0
0
21-47