Samsung S3C2451X User Manual page 128

STATIC MEMORY CONTROLLER
BANK WRITE ENABLE ASSERTION DELAY CONTROL REGISTERS 0-5
Register
SMBWSTWENR0 0x4F000010
SMBWSTWENR1 0x4F000030
SMBWSTWENR2 0x4F000050
SMBWSTWENR3 0x4F000070
SMBWSTWENR4 0x4F000090
SMBWSTWENR5 0x4F0000B
0
WSTWEN
NOTE: SMBWSTRDRx, SMBWSTWRRx, SMBWSTOENRx and SMBWSTWENRx registers are applied when
nWAIT signal is not used(WaitEn bit in SMBCRx is set to '0') . Otherwise, DRnOWE and DRnCS bits in SMBCRx
register are applied when nWAIT signal is used(WaitEn bit in SMBCRx is set to '1').
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
5-16
Specifications and information herein are subject to change without notice.
Address R/W
R/W Bank0 write enable assertion delay control register
R/W Bank1 write enable assertion delay control register
R/W Bank2 write enable assertion delay control register
R/W Bank3 write enable assertion delay control register
R/W Bank4 write enable assertion delay control register
R/W Bank5 write enable assertion delay control register
Bit
[31:4] Read undefined. Write as zero.
[3:0] Write enable assertion delay from chip select assertion. Default
to 0x2 at reset
S3C2451X RISC MICROPROCESSOR
Description
Description
Reset Value
0x2
0x2
0x2
0x2
0x2
0x2
Initial State
0x0
0x2