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S3C2451X RISC MICROPROCESSOR
IIS CONTROL REGISTER (IISCON)
Register
IISCON
IISCON
FTXURSTATUS
FTXURINTEN
LRI
FTXEMPT
FRXEMPT
FTXFULL
FRXFULL
TXDMAPAUSE
RXDMAPAUSE
TXCHPAUSE
Address
0x55000100
Bit
R/W
[31:18]
R/W
Reserved. Program to zero.
[17]
R/W
TX FIFO under-run interrupt status. And this is used by interrupt
clear bit. When this is high, you can do interrupt clear by writing '1'.
0 : Interrupt didn't be occurred.
1 : Interrupt was occurred.
[16]
R/W
TX FIFO Under-run Interrupt Enable
0: TXFIFO Under-run INT disable
1: TXFIFO Under-run INT enable
[15:12]
R/W
Reserved. Program to zero.
[11]
R
Left/Right channel clock indication. Note that LRI meaning is
dependent on the value of LRP bit of I2SMOD register.
0: Left (when LRP bit is low) or right (when LRP bit is high)
1: Right (when LRP bit is low) or left (when LRP bit is high)
[10]
R
Tx FIFO empty status indication.
0: FIFO is not empty (ready for transmit data to channel)
1: FIFO is empty (not ready for transmit data to channel)
[9]
R
Rx FIFO empty status indication.
0: FIFO is not empty
1: FIFO is empty
[8]
R
Tx FIFO full status indication.
0: FIFO is not full
1: FIFO is full
[7]
R
Rx FIFO full status indication.
0: FIFO is not full (ready for receive data from channel)
1: FIFO is full (not ready for receive data from channel)
[6]
R/W
Tx DMA operation pause command. Note that when this bit is
activated at any time, the DMA request will be halted after current
on-going DMA transfer is completed.
0: No pause DMA operation
1: Pause DMA operation
[5]
R/W
Rx DMA operation pause command. Note that when this bit is
activated at any time, the DMA request will be halted after current
on-going DMA transfer is completed.
0: No pause DMA operation
1: Pause DMA operation
[4]
R/W
Tx channel operation pause command. Note that when this bit is
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
IIS interface control register
Description
IIS-BUS INTERFACE
Reset Value
0x0000_0600
1)
25-15
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