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UART
UART Error Status FIFO
UART has the error status FIFO besides the Rx FIFO register. The error status FIFO indicates which data, among
FIFO registers, is received with an error. The error interrupt will be issued only when the data, which has an error,
is ready to read out. To clear the error status FIFO, the URXHn with an error and UERSTATn must be read out.
For example,
It is assumed that the UART Rx FIFO receives A, B, C, D and E characters sequentially and the frame error
occurs while receiving 'B', and the parity error occurs while receiving 'D'.
The actual UART receive error will not generate any error interrupt because the character which is received with
an error would have not been read. The error interrupt will occur once the character is read.
Figure 15-3 shows the UART receiving the five characters including the two errors.
Time
Sequence Flow
#0
When no character is read out
#1
A, B, C, D, and E is received
#2
After A is read out
#3
After B is read out
#4
After C is read out
#5
After D is read out
#6
After E is read out
Rx FIFO
'E'
'D'
'C'
'B'
'A'
Figure 15-3. Example showing UART Receiving 5 Characters with 2 Errors
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
15-6
Specifications and information herein are subject to change without notice.
The frame error (in B) interrupt occurs. The 'B' has to be read out.
The parity error (in D) interrupt occurs. The 'D' has to be read out.
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URXHn
Error Interrupt
–
–
–
–
–
Error Status FIFO
break error
UERSTATn
S3C2451 RISC MICROPROCESSOR
parity error
frame error
Error Status Generator Unit
Note
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