Samsung S3C2451X User Manual page 143

S3C2451X RISC MICROPROCESSOR
MOBILE DRAM TIMMING CONTROL REGISTER
Register
BANKCON2
TIMECON
Reserved [31:24]
tRAS [23:20]
tARFC [19:16]
Reserved [15:6]
CAS Latency [5:4]
tRCD [3:2]
tRP [1:0]
Address R/W
0x48000008 R/W
Bit
Reserved
Row active time
0000 = 1-clock 0001 = 2-clock 0010 = 3-clock 0011 = 4-clock
0100 = 5-clock 0101 = 6-clock 0110 = 7-clock 0111 = 8-clock
1000 = 9-clock 1001 = 10-clock 1010 = 11-clock 1011 = 12-clock
1100 = 13-clock 1101 = 14-clock 1110 = 15-clock 1111 = 16-clock
Self-refresh or Auto-refresh to next command cycle time
0000 = 1-clock 0001 = 2-clock 0010 = 3-clock 0011 = 4-clock
0100 = 5-clock 0101 = 6-clock 0110 = 7-clock 0111 = 8-clock
1000 = 9-clock 1001 = 10-clock 1010 = 11-clock 1011 = 12-clock
1100 = 13-clock 1101 = 14-clock 1110 = 15-clock 1111 = 16-clock
Reserved
CAS Latency Control
00 = Reserved 01 = 1-clock
RAS to CAS delay
00 = 1-clock
Row pre-charge time
00 = 1-clock
Description
Mobile DRAM timing control register
Description
10 = 2-clock
01 = 2-clock 10 = 3-clock
01 = 2-clock 10 = 3-clock
MOBILE DRAM CONTROLLER
Reset Value
0x0099_003F
Initial State
11 = 3-clock
11 = 4-clock
11 = 4-clock
0x00
1001b
1001b
0x000
011b
11b
11b
6-11