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S3C2451X RISC MICROPROCESSOR
WINDOW OPTION REGISTER 2
Register
CIDOWSFT2
0x4D80_0014
CIWDOFST2
Bit
Reserved
[31:27]
[26:16]
WinHorOfst2
Reserved
[15:11]
WinVerOfst2
[10:0]
Y1 START ADDRESS REGISTER
Register
CICOYSA1
0x4D80_0018
CICOYSA1
Bit
[31:0]
CICOYSA1
Y2 START ADDRESS REGISTER
Register
CICOYSA2
0x4D80_001C
CICOYSA2
Bit
[31:0]
CICOYSA2
Address
R/W
RW
Window horizontal offset2 by pixel unit. (It should be 2's
multiple)
Caution : SourceHsize-WinHorOfst- WinHorOfst2 should be
8's multiple.
Window vertical offset2 by pixel unit
Address
R/W
RW
Output format : YCbCr 4:2:2 or 4:2:0
address
Output format : RGB 16/24 bit
Address
R/W
RW
Output format : YCbCr 4:2:2 or 4:2:0
address
Output format : RGB 16/24 bit
address
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Window offset register 2
Description
Description
st
1
frame start address for codec DMA
Description
Y 1
st
RGB 1
Description
nd
2
frame start address for codec DMA
Description
Y 2
nd
RGB 2
CAMERA INTERFACE
st
frame start
frame start address
nd
frame start
frame start
Reset Value
0
Initial
Change
State
State
0
X
0
O
0
X
0
O
Reset Value
0
Initial
Change
State
State
0
X
Reset Value
0
Initial
Change
State
State
0
X
23-19
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