Samsung S3C2451X User Manual page 521

S3C2451X RISC MICROPROCESSOR
ENSIGBUFW
[4]
TRDY
ENSIGDMA [3]
ENSIGBLKG
[2]
AP
ENSIGSTAN
[1]
SCMPLT
ENSIGCMD
[0]
CMPLT
Buffer Write Ready Signal Enable
'1' = Enabled
'0' = Masked
DMA Interrupt Signal Enable
'1' = Enabled
'0' = Masked
Block Gap Event Signal Enable
'1' = Enabled
'0' = Masked
Transfer Complete Signal Enable
'1' = Enabled
'0' = Masked
Command Complete Signal Enable
'1' = Enabled
'0' = Masked
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
HSMMC CONTROLLER
0
0
0
0
0
21-53