Samsung S3C2451X User Manual page 240

INTERRUPT CONTROLLER
INTERRUPT MASK (INTMSK) REGISTER
This register also has 32 bits each of which is related to an interrupt source. If a specific bit is set to 1, the CPU
does not service the interrupt request from the corresponding interrupt source (note that even in such a case, the
corresponding bit of SRCPND register is set to 1). If the mask bit is 0, the interrupt request can be serviced.
Register
INTMSK1 0X4A000008
INTMSK2 0X4A000048
INTMSK1
INT_ADC
INT_RTC
INT_SPI1
INT_UART0
INT_IIC0
INT_USBH
INT_USBD
INT_NAND
INT_UART1
INT_SPI0
INT_SDI0
INT_SDI1
INT_CFCON
INT_UART3
INT_DMA
INT_LCD
INT_UART2
INT_TIMER4
INT_TIMER3
INT_TIMER2
INT_TIMER1
INT_TIMER0
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
10-14
Specifications and information herein are subject to change without notice.
Address R/W
R/W Determine which interrupt source of group 1is
masked. The masked interrupt source will not be
serviced.
0 = Interrupt service is available.
1 = Interrupt service is masked.
R/W Determine which interrupt source of group 2 is
masked. The masked interrupt source will not be
serviced.
0 = Interrupt service is available.
1 = Interrupt service is masked.
Bit
[31] 0 = Service available,
[30] 0 = Service available,
[29] 0 = Service available,
[28] 0 = Service available,
[27] 0 = Service available,
[26] 0 = Service available,
[25] 0 = Service available,
[24] 0 = Service available,
[23] 0 = Service available,
[22] 0 = Service available,
[21] 0 = Service available,
[20] 0 = Service available,
[19] 0 = Service available,
[18] 0 = Service available,
[17] 0 = Service available,
[16] 0 = Service available,
[15] 0 = Service available,
[14] 0 = Service available,
[13] 0 = Service available,
[12] 0 = Service available,
[11] 0 = Service available,
[10] 0 = Service available,
S3C2451X RISC MICROPROCESSOR
Description
Description
1 = Masked
1 = Masked
1 = Masked
1 = Masked
1 = Masked
1 = Masked
1 = Masked
1 = Masked
1 = Masked
1 = Masked
1 = Masked
1 = Masked
1 = Masked
1 = Masked
1 = Masked
1 = Masked
1 = Masked
1 = Masked
1 = Masked
1 = Masked
1 = Masked
1 = Masked
Reset Value
0xFFFFFFFF
0xFFFFFFFF
Initial State
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1