Samsung S3C2451X User Manual page 145

S3C2451X RISC MICROPROCESSOR
2) DDR2 memory MRS[15:0] and EMRS(1)[31:16]
PnBANKCON
BA [31:30]
Reserved
Qoff
RDQS
nDQS
OCD program [25:23]
Additive latency [21:19]
Rtt [22] [18]
D.I.C
DLL enable
Reserved [15:13]
Active Power
down exit time
WR [11:9]
DLL Reset
TM
CAS Latency
Burst Type
Burst Length
Bit
Bank address for EMRS
[29] Should be '0'
[28] 0 = Output buffer enable 1 = Output buffer disable
[27] 0 = Disable 1 = Enable
[26] 0 = Enable 1 = Disable
Refer to DDR2 spec.
Refer to DDR2 spec.
00 = ODT disable 01 = 75ohm 10 = 150ohm 11 = 50ohm
[17] 0 = Full strength 1 = Reduced strength
[16] 0 = Enable 1 = Disable
Should be '0'
[12] 0 = Fast exit 1 = Slow exit
Write recovery for auto pre-charge
[8] 0 = No 1 = Yes
[7] 0 = Normal 1 = Test
[6:4] CAS Latency for MRS
00 = Reserved 01 = 1-clock
[3] DRAM Burst Type (Read Only)
Only support sequential burst type.
[2:0] DRAM Burst Length (Read Only)
This value is determined internally.
Description
10 = 2-clock
MOBILE DRAM CONTROLLER
Initial State
000b
000b
000b
000b
000b
11 = 3-clock
011b
10b
0b
0b
0b
0b
00b
0b
0b
0b
0b
0b
0b
6-13