Samsung S3C2451X User Manual page 473

S3C2451X RISC MICROPROCESSOR
SD CLOCK STOP SEQUENCE
The flow chart for stopping the SD Clock is shown in Figure 21-4. The Host Driver shall not stop the SD Clock
when a SD transaction is occurring on the SD Bus -- namely, when either Command Inhibit (DAT) or Command
Inhibit (CMD) in the Present State register is set to 1.
(1) Set SD Clock Enable(ENSDCLK) in the Clock Control register to 0. Then, the Host Controller stops supplying
the SD Clock.
SD CLOCK FREQUENCY CHANGE SEQUENCE
The sequence for changing SD Clock frequency is shown in Figure 21-5. When SD Clock is still off, step (1) is
omitted.
(1)
Set SD Clock OFF
Figure 21-4SD Clock Stop Sequence
Figure 21-5 SD Clock Change Sequence
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
START
Stop SD Clock
END
HSMMC CONTROLLER
21-5