Samsung S3C2451X User Manual page 557

S3C2451X RISC MICROPROCESSOR
2BPP display (Palette)
(BSWP = 0, HWSWP = 0)
[31:30]
002H P1
006H P17
00AH P33
...
[15:14]
000H P9
004H P25
008H P41
...
1BPP display (Palette)
(BSWP = 0, HWSWP = 0)
[31] [30]
002H P1 P2
006H P33 P34
...
[15] [14]
000H P17 P18
004H P49 P50
...
NOTE: The values of frame buffer are index of palette memory.
The MSB value of Palette memory is AEN bit.
AEN : Select Alpha value in Window 1 Alpha Value Register for alpha blending
AEN = 0 : ALPHA0_R/G/B values are applied.
AEN = 1 : ALPHA1_R/G/B values are applied.
Each pixel of LCD panel displays blended color with lower layer window.
Refer to the equation of alpha blending on page 22-22.
[29:28] [27:26]
P2
P18 P19
P34 P35
[13:12] [11:10]
P10 P11
P26 P27
P42 P43
[29] [28] [27] [26]
P3 P4 P5 P6
P35 P36 P37 P38
[13] [12] [11] [10]
P19 P20 P21 P22
P51 P52 P53 P54
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
[25:24] [23:22]
P3 P4
P20
P36
[9:8]
P12
P28
P44
[25] [24] [23]
P7 P8 P9
P39 P40 P41
[9] [8] [7]
P23 P24 P25
P55 P56 P57
[21:20]
P5 P6
P21 P22
P37 P38
[7:6] [5:4]
P13 P14
P29 P30
P45 P46
[22] [21] [20] [19]
P10 P11 P12 P13
P42 P43 P44 P45
[6] [5] [4] [3]
P26 P27 P28 P29
P58 P59 P60 P61
LCD CONTROLLER
[19:18] [17:16]
P7 P8
P23 P24
P39 P40
[3:2] [1:0]
P15 P16
P31 P32
P47 P48
[18] [17] [16]
P14 P15 P16
P46 P47 P48
[2] [1] [0]
P30 P31 P32
P62 P63 P64
22-17