Samsung S3C2451X User Manual page 658

IIS-BUS INTERFACE
EXAMPLE CODE
TX CHANNEL
The I2S TX channel provides a single stereo compliant output. The transmit channel can operate in master or
Slave mode. Data is transferred between the processor and the I2S controller via an APB access or a DMA
access.
The processor must write words in multiples of two (i.e. for left and right audio sample).The words are
serially shifted out timed with respect to the audio serial bitclk, SCLK and word select clock, LRCLK.
TX Channel has 16X32 bit wide FIFO where the processor or DMA can write upto 16 left/right data samples
After enabling the channel for transmission.
An Example sequence is as the following.
Ensure the PCLK and CLKAUDIO are coming correctly to the I2S controller and FLUSH the TX FIFO using
the TFLUSH bit in the
Please ensure that I2S Controller is configured in one of the following modes.
•
TX only mode
•
TX/RX simultaneous mode
This can be done by programming the TXR bit in the I2SMOD Register (I2S Mode Register).
1. Then Program the following parameters according to the need
•
IMS
•
SDF
•
BFS
•
BLC
•
LRP
For Programming, the above-mentioned fields please refer I2SMOD Register (I2S Mode Register).
2. Once ensured that the input clocks for I2S controller are up and running and step 1 and 2 have been
completed we can write to TX FIFO.
The write to the TX FIFO has to be carried out thorough the I2STXD Register (I2S TX FIFO Register)
This 32 bit data will occupy position 0 of the FIFO and any further data will be written to position 2, 3 and so
on.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
25-8
Specifications and information herein are subject to change without notice.
S3C2451X RISC MICROPROCESSOR