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SYSTEM CONTROLLER
POWER SAVING MODES
S3C2451 can support various power saving modes. These are Normal mode, Idle mode, Stop mode, Deep-sotp
mode and Sleep mode.
Normal Mode (General Clock Gating Mode)
In General Clock Gating mode, the On/Off clock gating of the individual clock source of each IP block is performed
by controlling of each corresponding clock source enable bit. The Clock Gating is applied instantly whenever the
corresponding bit (or bits) is changed. (Ithese bits are set or cleared by the main CPU.)
IDLE Mode
In IDLE mode, the clock to CPU core is stopped. To enter the idel mode, User configure system controller's
special register. The IDLE mode is activated just after the execution of the STORE instruction that enables the
IDLE Mode bit. In that case the IDLE Mode bit should be cleared after the wake-up from the IDLE state for the
entering of next IDLE Mode. The H/W logic only detects the low-to-high triggering of the IDLE Mode bit.
STOP mode (Normal and Deep-stop)
In STOP mode, all clocks are stopped for minimum power consumption. Therefore, the PLL and oscillator circuit
are also stopped(oscillator circuit is stopped optionally, see PWRCFG register). The STOP Mode is activated after
the execution of the STORE instruction that enables the STOP Mode bit. The STOP Mode bit should be cleared
after the wake-up from the STOP state for the entering of next STOP Mode. The H/W logic only detects the low-
to-high triggering of the STOP Mode bit.
In Deep-STOP mode ARM core's power is off by using internal power gating. By this way, the static current will be
reduced remarkably compared with STOP mode. To enter the Deep-STOP mode, PWRMODE[18] register should
be configured before entering STOP mode. After waking up from Deep-STOP mode, System controller resets
ARM core only.
To exit from STOP mode, External interrupt, RTC alarm, RTC Tick, or nRESET has to be activated. During the
wake-up sequences, the crystal oscillator and PLL may begin to operate. The crystal-oscillator settle-down-time
and the PLL locking-time is required to provide stabilized ARMCLK. Those time-waits are automatically inserted
by the hardware of S3C2451X. During these time-waits, the clock is not supplied to the internal logic circuitry.
STOP mode Entering sequence is as follows
1.
Set the STOP Mode bit ( by the main CPU)
2.
System controller requests bus controller to finish bus transactions of ARM Core.
3.
System controller disable ARM clock after getting ARM Down acknowledge.
4.
System controller requests bus controller to finish current transactions.
5.
Bus controller send acknowledge to system controller after completed bus transactions.
6.
System controller request memory controller to enter self refresh mode. It is for preserving contents in
SDRAM.
7.
System controller wait for self refresh acknowledge from memory controller.
8.
After receiving the self-refresh acknowledge, system controller disables system clocks, and switches
SYSCLK's source to MPLL reference clock.
9.
Disables PLLs and Crystal(XTI) oscillation. If OSC_EN_STOP bit in PWRCFG register is 'high' then
system controller doesn't disable crystal oscillation.
10. When PWRMODE[18] register is configured as '1' (Deep-STOP Enabled), ARM_PWRENn signal change
to enable ARM power gating. ARM Core is reset state during STOP mode.
Preliminary product information describe products that are in development,
2-14
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
S3C2451X RISC MICROPROCESSOR
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