Samsung S3C2451X User Manual page 36

PRODUCT OVERVIEW
Signal
DP_UDEV
REXT
XO_UDEV
XI_UDEV
SPI
SPIMISO[1:0]
SPIMOSI[1:0]
SPICLK[1:0]
nSS[1:0]
SDMMC Interface
SD1_DAT[7:0]
SD1_CMD
SD1_CLK
SD1_nWP
SD1_nCD
SD1_nLED
SD0_DAT[3:0]
SD0_CMD
SD0_CLK
General Port
GPn[147:0]
TIMMER/PWM
TOUT[3:0]
TCLK
JTAG TEST
LOGIC
nTRST
TMS
TCK
TDI
TDO
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
1-32
Specifications and information herein are subject to change without notice.
In/Out
IO DATA(+) for USB peripheral.
O External Resistor ( 44.2ohm +/- 1%)
OSC Crystal output
OSC Crystal input
IO SPIMISO is the master data input line, when SPI is configured as a master.
When SPI is configured as a slave, these pins reverse its role.
IO SPIMOSI is the master data output line, when SPI is configured as a master.
When SPI is configured as a slave, these pins reverse its role.
IO SPI clock
I SPI chip select (only for slave mode)
IO SD1 receive/transmit data
IO SD1 receive response/ transmit command
O SD1 clock
O SD1 Write Protect
O SD1 Card Detect
O SD1 LED
IO SD0 receive/transmit data
IO SD0 receive response/ transmit command
O SD0 clock
IO General input/output ports, which are multiplexed with other function pins
(some ports are output only).
O Timer output[3:0]
I External timer clock input
I nTRST (TAP Controller Reset) resets the TAP controller at start.
If debugger is used, A 10K pull-up resistor has to be connected.
If debugger (black ICE) is not used, nTRST pin must be issued by a low active
pulse (Typically connected to nRESET).
I TMS (TAP Controller Mode Select) controls the sequence of the TAP
controller's states.
I TCK (TAP Controller Clock) provides the clock input for the JTAG logic.
I TDI (TAP Controller Data Input) is the serial input for test instructions and
data.
O TDO (TAP Controller Data Output) is the serial output for test instructions and
data.
S3C2451X RISC MICROPROCESSOR
Description