S3C2451X RISC MICROPROCESSOR
SMCLK
ADDR
nCS
nWE
nWAIT
DATA ( W )
SMCLK
ADDR
nCS
nWE
nWAIT
DATA ( W )
Figure 5-9. Write Timing Diagram (DRnCS = 1, DRnOWE = 0)
Figure 5-10. Write Timing Diagram (DRnCS = 1, DRnOWE = 1)
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
STATIC MEMORY CONTROLLER
A
D ( A )
A
D ( A )
5-9