Samsung S3C2451X User Manual page 418

IIC-BUS INTERFACE
MULTI-MASTER IIC-BUS CONTROL/STATUS (IICSTAT) REGISTER
Register
IICSTAT0 0x54000004
IICSTAT1 0x54000104
IICSTAT0
Bit
IICSTAT1
Mode selection [7:6]
Busy signal [5]
status /
START STOP
condition
Serial output [4]
Arbitration status [3]
flag
Address-as- [2]
slave status flag
Address zero [1]
status flag
Last-received bit [0]
status flag
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
18-12
Specifications and information herein are subject to change without notice.
Address R/W
R/W IIC0-Bus control/status register
R/W IIC1-Bus control/status register
IIC-bus master/slave Tx/Rx mode select bits.
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
IIC-Bus busy signal status bit.
0: read) Not busy (when read)
write) STOP signal generation
1: read) Busy (when read)
write) START signal generation.
The data in IICDS will be transferred
automatically just after the start signal.
IIC-bus data output enable/disable bit.
0: Disable Rx/Tx,
IIC-bus arbitration procedure status flag bit.
0: Bus arbitration successful
1: Bus arbitration failed during serial I/O
IIC-bus address-as-slave status flag bit.
0: Cleared after reading of IICSTAT register
1: Received slave address matches the address value in the
IICADD
IIC-bus address zero status flag bit.
0: Cleared when START/STOP condition was detected
1: Received slave address is 00000000b.
IIC-bus last-received bit status flag bit.
0: Last-received bit is 0 (ACK was received).
1: Last-received bit is 1 (ACK was not received).
Description
Description
1: Enable Rx/Tx
S3C2451X RISC MICROPROCESSOR
Reset Value
Initial State
0x0
0x0
00
0
0
0
0
0
0