Samsung S3C2451X User Manual page 463

S3C2451X RISC MICROPROCESSOR
RxTrigger
TxTrigger
reserved
RxDMA On
TxDMA On
DMA transfer
** Channel Transfer size must be smaller than Bus Transfer size or the same as.
Register
Slave_slection_reg(Ch0)
Slave_slection_reg(Ch1)
Slave_slection_reg
nCS_time_count
reserved
Auto_n_Manual
nSSout
Register
HS_SPI_INT_EN(Ch0)
HS_SPI_INT_EN(Ch1)
R/W Rx FIFO trigger level in INT mode.
[16:11]
Trigger level is from 0 to 63. The value means
byte number in RX FIFO
R/W
[10:5] Tx FIFO trigger level in INT mode
Trigger level is from 0 to 63. The value means
byte number in TX FIFO
-
[4:3]
R/W
[2] DMA mode on/off
0 : DMA mode off
R/W
[1] DMA mode on/off
0 : DMA mode off
R/W
[0] DMA transfer type, single or 4 bust.
0 : single
DMA transfer size should be set as the same
size in DMA as it in HS_SPI.
Address R/W
0x5200000C R/W
0x5900000C R/W
Bit
nSSout inactive time =
R/W
[9:4]
((nCS_time_count+3)/2) x HS_SPICLKout)
-
[3:2]
Chip select toggle manual or auto selection
R/W
[1]
R/W
[0]
Address R/W
0x52000010 R/W
0x59000010 R/W
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
-
1 : DMA mode on
Description
Slave selection signal
Slave selection signal
Description
reserved
0: manual
Slave selection signal( manual only)
0: active
Description
HS_SPI Interrupt Enable register
HS_SPI Interrupt Enable register
HS_SPI CONTROLLER
1 : DMA mode on
1 : 4 burst
Reset Value
Initial State
1: Auto
1: inactive
Reset Value
6'b0
6'b0
-
1'b0
1'b0
1'b0
0x1
0x1
6'b0
-
1'b0
1'b1
0x0
0x0
20-7