Samsung S3C2451X User Manual page 543

S3C2451X RISC MICROPROCESSOR
FUNCTIONAL DESCRIPTION
BRIEF OF THE SUB-BLOCK
The LCD controller consists of a VSFR, VDMA, VPRCS, VTIME, and video clock generator. The VSFR has 71
programmable register sets and two-256x25 palette memory, which are used to configure the LCD controller. The
VDMA is a dedicated LCD DMA, which it can transfer the video data in frame memory to VPRCS. By using this
special DMA, the video data can be displayed on the screen without CPU intervention. The VPRCS receives the
video data from VDMA and sends the video data through the data ports (RGB_VD, VEN_VD, or SYS_VD ) to the
display device (LCD) after changing them into a suitable data format, for example 8-bit per pixel mode (8 BPP
Mode) or 16-bit per pixel mode (16 BPP Mode). The VTIME consists of programmable logic to support the
variable requirement of interface timing and rates commonly found in different LCD drivers. The VTIME block
generates RGB_VSYNC, RGB_HSYNC, RGB_VCLK, RGB_VDEN, SYS_CS1, SYS_CS0, and so on.
DATA FLOW
FIFO is present in the VDMA. When FIFO is empty or partially empty, VDMA requests data fetching from the
frame memory based on the burst memory transfer mode(Consecutive memory fetching of 4 / 8 / 16 words per
one burst request without allowing the bus mastership to another bus master during the bus transfer). When bus
arbitrator in the memory controller accepts this kind of transfer request, there will be 4 /8 /16 successive word data
transfers from system memory to internal FIFO. The each size of FIFO is 32 words. The LCD controller has two
FIFOs because it needs to support the overlay window mode. In case of one screen display mode, the only one
FIFO should be used. The data through FIFO is fetched by VPRCS which has a blending, scheduling function for
the final image data. VPRCS supports overlay function that enables to overlay any image up to 2 window images
whose is smaller or same size can be blended with main window image with programmable alpha blending or
color (chroma) key function. Fig. 22-2 shows the data flow from system bus to the output buffer. VDMA has two
DMA channels. Alpha values written in SFR determine the level of blending. Data from Output buffer will be
appearing to the Video Data Port.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
LCD CONTROLLER
22-3