Samsung S3C2451X User Manual page 670

IIS-BUS INTERFACE
IIS TRANSMIT REGISTER (IISTXD)
Register
IISTXD
IISTXD
IISTXD
IIS RECEIVE REGISTER (IISRXD)
Register
IISRXD
IISRXD
IISRXD
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
25-20
Specifications and information herein are subject to change without notice.
Address
0x55000110
Bit R/W
[31:0] W
TX FIFO write data. Note that the left/right channel data is allocated
as the following bit fields.
R[23:0], L[23:0] when 24-bit BLC
R[31:16], L[15:0] when 16-bit BLC
R[23:16], L[7:0] when 8-bit BLC
Address
0x55000114
Bit R/W
[31:0] R
RX FIFO read data. Note that the left/right channel data is allocated
as the following bit fields.
R[23:0], L[23:0] when 24-bit BLC
R[31:16], L[15:0] when 16-bit BLC
R[23:16], L[7:0] when 8-bit BLC
Description
IIS interface transmit data register
Description
Description
IIS interface receive data register
Description
S3C2451X RISC MICROPROCESSOR
Reset Value
0x0000_0000
Reset Value
0x0000_0000