Samsung S3C2451X User Manual page 215

S3C2451X RISC MICROPROCESSOR
EXAMPLES OF POSSIBLE CASES
Single service, Demand Mode, Single Transfer Size
The assertion of XnXDREQ is need for every unit transfer (Single service mode), the operation continues while
the XnXDREQ is asserted(Demand mode), and one pair of Read and Write(Single transfer size) is performed.
XSCLK
XnXDREQ XnXDREQ
XnXDACK XnXDACK
Double
synch
Single service/Handshake Mode, Single Transfer Size
XSCLK
XnXDREQ
XnXDACK
Double
synch
Figure 9-5. Single service, Handshake Mode, Single Transfer Size
Whole service/Handshake Mode, Single Transfer Size
XSCLK
XnXDREQ
XnXDACK
Double
synch
Figure 9-6. Whole service, Handshake Mode, Single Transfer Size
Read Write
Figure 9-4. Single service, Demand Mode, Single Transfer Size
3 cycles
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
2cycles
Read Write
2cycles
Read Write
DMA CONTROLLER
Read Write
2cycles
Read Write Read
Read Write
Write
9-7