Samsung S3C2451X User Manual page 494

HSMMC CONTROLLER
RESPONSE REGISTER
This register is used to store responses from SD cards.
Register
RSPREG0_0
RSPREG1_0
RSPREG2_0
RSPREG3_0
Register
RSPREG0_1
RSPREG1_1
RSPREG2_1
RSPREG3_1
Name Bit
[127:0] Command Response
CMDRS
The Table below describes the mapping of command responses from the SD
P
Bus to this register for each response type. In the table, R[] refers to a bit range
within the response data as transmitted on the SD Bus, REP[] refers to a bit
range within the Response register.
128-bit Response bit order : {RSPREG3, RSPREG2, RSPREG1, RSPREG0}
Kind of Response
R1, R1b (normal response)
R1b (Auto CMD12 response)
R2 (CID, CSD register)
R3 (OCR register)
R4 (OCR register)
R5,R5b
R6 (Published RCA response)
R7
The Response Field indicates bit positions of "Responses" defined in the PHYSICAL LAYER SPECIFICATION
Version 1.01. The Table (upper) shows that most responses with a length of 48 (R[47:0]) have 32 bits of the
response data (R[39:8]) stored in the Response register at REP[31:0]. Responses of type R1b (Auto CMD12
responses) have response data bits R[39:8] stored in the Response register at REP[127:96]. Responses with
length 136 (R[135:0]) have 120 bits of the response data (R[127:8]) stored in the Response register at
REP[119:0].
To be able to read the response status efficiently, the Host Controller only stores part of the response data in the
Response register. This enables the Host Driver to efficiently read 32 bits of response data in one read cycle on a
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
21-26
Specifications and information herein are subject to change without notice.
Address
0X4AC00010
0X4AC00014
0X4AC00018
0X4AC0001C
Address
0X4A800010
0X4A800014
0X4A800018
0X4A80001C
Meaning of Response
Card Status
Card Status for Auto CMD12
CID or CSD reg. incl.
OCR register for memory
OCR register for I/O etc
SDIO response
New published RCA[31:16] etc
?
Response Bit Definition for Each Response Type.
R/W Description
ROC Response Register 0 (Channel 0)
ROC Response Register 1 (Channel 0)
ROC Response Register 2 (Channel 0)
ROC Response Register 3 (Channel 0)
R/W Description
ROC Response Register 0 (Channel 1)
ROC Response Register 1 (Channel 1)
ROC Response Register 2 (Channel 1)
ROC Response Register 3 (Channel 1)
Description
Response Field
R [39:8]
R [39:8]
R [127:8]
R [39:8]
R [39:8]
R [39:8]
R [39:8]
R [39:8]
S3C2451X RISC MICROPROCESSOR
Reset Value
Reset Value
Response Register
REP [31:0]
REP [127:96]
REP [119:0]
REP [31:0]
REP [31:0]
REP [31:0]
REP [31:0]
REP [31:0]
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Initial
Value