Samsung S3C2451X User Manual page 120

STATIC MEMORY CONTROLLER
ASYNCHRONOUS WRITE
You can program the delay between the assertion of the chip select and the write enable from 0-15 cycles using
the WSTWEN bits of the Bank Write Enable Assertion Delay Control Register, SMBWSTWENRx. This reduces
the power consumption for memories. The write enable is asserted on the rising edge of nSMMEMCLK, half a
clock after the assertion of chip select.
For most asynchronous memory devices an SMMEMCLK cycle is required before the assertion of nWE otherwise
there is the hazard that nCS changes after nWE. You can add extra cycles before nWE is asserted using the
WSTWEN bits in the Bank Write Enable Assertion Delay Control Registers. For example, setting
WSTWR=WSTWEN=1 extends the transfer by one cycle and delays the assertion of nWE by one cycle.
The Write enable is always deasserted half a cycle before the chip select, at the end of the transfer. nSMBLS has
the same timing as nSMWEN for writes to 8-bit devices that use the byte lane selects instead of the write enables.
The WSTWEN programmed value must be equal to, or less than the WSTWR programmed value otherwise an
invalid access sequence is generated. The access is timed by the WSTWR value and not by the WSTWEN value.
In the External Wait enabled mode, the timing of the transfer (controlled by SMWAIT) is not known. WSTWEN still
delays the assertion of nSMWEN. nSMWEN is delayed more by the external wait signal if it has not been
asserted when SMWAIT is asserted.
You might require the SMADDRVALID signal for synchronous static memory devices when you use it in
asynchronous mode. You can disable it using the AddrValidWriteEn bit in the SMBCRx Register. This bit defaults
to being set(enable). You can then clear it if you do not require it. When you disable it, the signal is driven HIGH
continuously.
Figure 5-8 shows a single external memory write transfer with two write enable delay states, WSTEN=2, and two
wait states, WSTWR=2. A single AHB wait state is inserted.
SMCLK
ADDR
DATA(OUT)
nCS
SMAVD
nWE
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
5-8
Specifications and information herein are subject to change without notice.
Asynchronous Write
Figure 5-8. External Memory Two Write Enable Delay State Write
D(A)
WSTWR=2
WSTWEN=2
S3C2451X RISC MICROPROCESSOR
A