Pcm0_Sdo; Pcm0_Sdi; Pcm0_Cdclk; Pcm0_Sclk - Samsung S3C2451X User Manual

S3C2451X RISC MICROPROCESSOR
PORT E CONTROL REGISTERS (GPECON, GPEDAT, GPEUDP, GPESEL) (Continued)
GPEDAT
Reserved
GPE[15:0]
GPEUDP
GPEUDP15
~
GPEUDP0
GPESEL
Reserved
GPE4SEL
GPE3SEL
GPE2SEL
GPE1SEL
GPE0SEL
Bit
[31:16] Reserved
[15:0] When the port is configured as an input port, the corresponding bit is the pin
state. When the port is configured as an output port, the pin state is the
same as the corresponding bit.
When the port is configured as a functional pin, the undefined value will be
read.
Bit
[CPU:CPD]
[31:30]
~
00 : pull-up/down disable
[1:0]
01 : pull-down enable
10 : pull-up enable
11 : not-available
Bit
[31:5] Reserved
[4] 0 = GPE4
[3] 0 = GPE3
[2] 0 = GPE2
[1] 0 = GPE1
[0] 0 = GPE0
Description
Description
Description

1 = PCM0_SDO

1 = PCM0_SDI

1 = PCM0_CDCLK

1 = PCM0_SCLK

1 = PCM0_FSYNC
I/O PORTS
11-19