Samsung S3C2451X User Manual page 95

S3C2451X RISC MICROPROCESSOR
The special clocks are controlled by SCLKCON register. Some blocks in the device require several operating
frequencies, i.e., 48 MHz and 24 MHz for USB interface block. Thus, these output frequencies can be controlled
by the CLKDIV values.
SCLKCON
RESERVED
SPICLK_MPLL1
SPICLK_MPLL0
PCM1_EXT
PCM0_EXT
DDRCLK(Hx2CLK)
SSMCCLK(HX1_2CLK)
SPICLK_0
HSMMCCLK_EXT
HSMMCCLK_1
CAMCLK
DISPCLK
I2SCLK_0
UARTCLK
SPICLK_1
HSMMCCLK_0
I2SCLK_1
RESERVED
USB HOST
RESERVED
Bit
[31:21] -
[20] Enable SPICLK1 (MPLL)
[19] Enable SPICLK0 (MPLL)
[18] Enable PCM1 External Clock
[17] Enable PCM0 External Clock
[16] Enable DDRCLK
[15] Enable SSMCCLK
[14] Enable HS-SPI_0 (EPLL) clock
Enable HSMMC_EXT clock for HSMMC0, 1 (EXTCLK)
[13]
Reference clock of MPLL
Enable HSMMC1_1 clock for (from EPLL or USB48M
[12]
output)
[11] Enable CAM clock
[10] Enable display controller clock
[9] Enable I2S_0 clock
[8] Enable UART clock
[7] Enable HS-SPI_1 (EPLL) clock
Enable HSMMC_0 clock for (from EPLL or USB48M
[6]
output)
[5] Enable I2S_1 clock
[4:2] -
[1] Enable USB HOST clock
[0] -
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
SYSTEM CONTROLLER
Initial
Value
0x7FF
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0x7
1
1
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