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S3C2451X RISC MICROPROCESSOR
PCM R
FIFO REGISTER
X
Register
PCM_RXFIFO0
PCM_RXFIFO1
The bit definitions for the PCM_RXFIFO Register are shown below:
PCM_RXFIFOn
Reserved
RXFIFO_DVALID
RXFIFO_DATA
Address
R/W
0x5C00000C
R/W
0x5C00010C
R/W
Bit
[31:17]
Reserved
[16]
RXFIFO data is valid
Write: don't care
Read: TXFIFO read data valid
1: valid
0: invalid (probably read an empty fifo)
[15:0]
Write: Write PCM data to RXFIFO for debugging RXFIFO
Read: Read PCM data from RXFIFO
NOTE: the RXFIFO is written by the PCM serial shift engine
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
PCM0 interface Receive FIFO data
register
PCM1 interface Receive FIFO data
register
Description
PCM AUDIO INTERFACE
Reset Value
0x00010000
0x00010000
Initial
State
1
0
28-11
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