Samsung S3C2451X User Manual page 212

DMA CONTROLLER
EXTERNAL DMA DREQ/DACK PROTOCOL
There are four types of external DMA request/acknowledge protocols. Each type defines how the signals like
DMA request and acknowledge are related to these protocols.
Basic DMA Timing
The DMA service means paired Reads and Writes cycles during DMA operation, which is one DMA operation.
The Figure. 9-1 shows the basic Timing in the DMA operation of the S3C2451X.
•
The setup time and the delay time of XnXDREQ and XnXDACK are same in all the modes.
•
If the completion of XnXDREQ meets its setup time, it is synchronized twice and then XnXDACK is asserted.
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After assertion of XnXDACK, DMA requests the bus and if it gets the bus it performs its operations. XnXDACK
is deasserted when DMA operation finishes.
XSCLK
XnXDREQ
XnXDACK
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
9-4
Specifications and information herein are subject to change without notice.
9.3ns Setup
Min. 2MCLK
Min. 3MCLK
6.8ns Delay
Figure 9-1. Basic DMA Timing Diagram
S3C2451X RISC MICROPROCESSOR
9.3ns Setup
6.6ns Delay
Read Write