Samsung S3C2451X User Manual page 525

S3C2451X RISC MICROPROCESSOR
CAPABILITIES REGISTER
This register provides the Host Driver with information specific to the Host Controller implementation. The
Host Controller may implement these values as fixed or loaded from flash memory during power on
initialization. Refer to Software Reset For All in the Software Reset register for loading from flash memory
and completion timing control.
Register
CAPAREG0
CAPAREG1
Name Bit
[31:27]
[26]
CAPAV18
[25]
CAPAV30
[24]
CAPAV33
CAPASUS
[23]
RES
CAPADM
[22]
A
CAPAHSP
[21]
D
[20:18]
CAPAMAX
[17:16]
BLKLEN
[15:14]
Address
0X4AC00040
0X4A800040
Reserved
Voltage Support 1.8V (HWInit)
'1'=1.8V Supported
'0'=1.8V Not Supported
Voltage Support 3.0V (HWInit)
'1'=3.0V Supported
'0'=3.0V Not Supported
Voltage Support 3.3V (HWInit)
'1'=3.3V Supported
'0'=3.3V Not Supported
Suspend/Resume Support (HWInit)
This bit indicates whether the Host Controller supports Suspend /
Resume functionality. If this bit is 0, the Suspend and Resume
mechanism are not supported and the Host Driver shall not issue either
Suspend or Resume commands.
'1'=Supported
'0'=Not Supported
DMA Support (HWInit)
This bit indicates whether the Host Controller is capable of using DMA to
transfer data between system memory and the Host Controller directly.
'1'=DMA Supported
'0'=DMA Not Supported
High Speed Support (HWInit)
This bit indicates whether the Host Controller and the Host System
support High Speed mode and they can supply SD Clock frequency from
25MHz to 50MHz.
'1'=High Speed Supported
'0'= High Speed Not Supported
Reserved
Max Block Length (HWInit)
This value indicates the maximum block size that the Host Driver can
read and write to the buffer in the Host Controller. The buffer shall
transfer this block size without wait cycles. Three sizes can be defined as
indicated below.
'00'=512-byte, '01'=1024-byte, '10'=2048-byte, '11'=Reserved
Reserved
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
R/W
HWInit Capabilities Register (Channel 0)
HWInit Capabilities Register (Channel 1)
Description
HSMMC CONTROLLER
Description Reset Value
0x05E80080
0x05E80080
Initial Value
1
0
1
1
1
1
0
0
21-57