Samsung S3C2451X User Manual page 512

HSMMC CONTROLLER
NORMAL INTERRUPT STATUS REGISTER
The Normal Interrupt Status Enable affects reads of this register, but Normal Interrupt Signal Enable does not
affect these reads. An interrupt is generated when the Normal Interrupt Signal Enable is enabled and at least one
of the status bits is set to 1. For all bits except Card Interrupt and Error Interrupt, writing 1 to a bit clear it; writing
to 0 keeps the bit unchanged. More than one status can be cleared with a single register write. The Card
Interrupt is cleared when the card stops asserting the interrupt; that is, when the Card Driver services the
interrupt condition.
Register
NORINTSTS0 0X4AC00030
NORINTSTS1 0X4A800030
Name Bit
STAERR [15]
STAFIA3 [14]
STAFIA2 [13]
STAFIA1 [12]
STAFIA0 [11]
STARWAIT [10]
STACCS [9]
STACARDI [8]
NT
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
21-44
Specifications and information herein are subject to change without notice.
Address R/W
ROC/RW1C
ROC/RW1C
Error Interrupt
If any of the bits in the Error Interrupt Status register are set, then this bit is
set. Therefore the Host Driver can efficiently test for an error by checking this
bit first. This bit is read only. (ROC)
'0' = No Error
'1' = Error
FIFO SD Address Pointer Interrupt 3 Status (RW1C)
'0' = Occurred
'1' = Not Occurred
FIFO SD Address Pointer Interrupt 2 Status (RW1C)
'0' = Occurred
'1' = Not Occurred
FIFO SD Address Pointer Interrupt 1 Status (RW1C)
'0' = Occurred
'1' = Not Occurred
FIFO SD Address Pointer Interrupt 0 Status (RW1C)
'0' = Occurred
'1' = Not Occurred
Read Wait Interrupt Status (RW1C)
'0' = Read Wait Interrupt Occurred
'1' = Read Wait Interrupt Not Occurred
Note : After checking response for the suspend command, release Read Wait
interrupt status manually if BS = 0
CCS Interrupt Status (RW1C)
Command Complete Singal Interrupt Status bit is for CE-ATA interface mode.
'0' = CCS Interrupt Occurred
'1' = CCS Interrupt Not Occurred
Card Interrupt
Writing this bit to 1 does not clear this bit. It is cleared by resetting the SD
card interrupt factor. In 1-bit mode, the Host Controller shall detect the Card
Interrupt without SD Clock to support wakeup. In 4-bit mode, the card
interrupt signal is sampled during the interrupt cycle, so there are some
sample delays between the interrupt signal from the SD card and the interrupt
Description
Normal Interrupt Status Register (Channel 0)
Normal Interrupt Status Register (Channel 1)
Description
S3C2451X RISC MICROPROCESSOR
Reset Value
0x0
0x0
Initial
Value
0
0
0
0
0
0
0
0